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19-2332; Rev 1; 9/03
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference
General Description
The MAX5230/MAX5231 low-power, dual 12-bit voltageoutput digital-to-analog converters (DACs) feature an internal 3ppm/C precision bandgap voltage reference and precision output amplifiers. The MAX5231 operates on a single 5V supply with an internal 2.5V reference and features a 4.095V full-scale output range. The MAX5230 operates on a single 3V supply with an internal 1.25V reference and features a 2.0475V full-scale output range. The MAX5231 consumes only 470A while the MAX5230 consumes only 420A of supply current. Both devices feature low-power (2A) software- and hardwareenabled shutdown modes. The MAX5230/MAX5231 feature a 13.5MHz SPITM-, QSPITM-, and MICROWIRETM-compatible 3-wire serial interface. An additional data output (DOUT) allows for daisy-chaining and read back. Each DAC has a doublebuffered digital input. The MAX5230/MAX5231 feature two software-selectable shutdown output impedances: 1k or 200k. A power-up reset feature sets DAC outputs at ground or at the midscale DAC code. The MAX5230/MAX5231 are specified over the extended temperature range (-40C to +85C) and are available in 16-pin QSOP packages.
Features
o Internal 3ppm/C Precision Bandgap Reference 2.465V (MAX5231) 1.234V (MAX5230) o 10ppm/C (max) Full-Scale Output Range 4.095V (MAX5231) 2.0475V (MAX5230) o Single-Supply Operation 5V (MAX5231) 3V (MAX5230) o Low Supply Current 470A (MAX5231) 420A (MAX5230) o 13.5MHz SPI/QSPI/MICROWIRE-Compatible, 3-Wire Serial Interface o Pin-Programmable Power-Up Reset State to Zero or Midscale Output Voltage o Programmable Shutdown Modes with 1k or 200k Internal Output Loads o Recalls Output State Prior to Shutdown or Reset o Buffered Output Drives 5k || 100pF Loads o Space-Saving 16-Pin QSOP Package
MAX5230/MAX5231
Applications
Industrial Process Controls Automatic Test Equipment Digital Offset and Gain Adjustment Motion Control P-Controlled Systems
Ordering Information
PART MAX5230AEEE MAX5230BEEE MAX5231AEEE MAX5231BEEE TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 16 QSOP 16 QSOP 16 QSOP 16 QSOP INL (LSB) 0.5 1 0.5 1
Pin Configuration
TOP VIEW
OSA 1 OUTA 2 RSTV 3 LDAC 4 CLR 5 CS 6 DIN 7 SCLK 8 16 OSB 15 OUTB 14 VDD
Functional Diagram appears at end of data sheet. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor, Corp.
MAX5230 MAX5231
13 AGND 12 REF 11 PDL 10 DOUT 9 DGND
QSOP
________________________________________________________________ Maxim Integrated Products
1
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3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference MAX5230/MAX5231
ABSOLUTE MAXIMUM RATINGS
VDD to AGND, DGND ...............................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V Digital Inputs to DGND.............................................-0.3V to +6V Digital Output (DOUT) to DGND...................-0.3V to VDD + 0.3V OUT_ to AGND .............................................-0.3V to VDD + 0.3V OS_ to AGND...................................................-4V to VDD + 0.3V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 16-Pin QSOP (derate 8.3mW/C above +70C)...........667mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--MAX5231
(VDD = +4.5V to +5.5V, OS_ = AGND = DGND = 0, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity Offset Error (Note 2) Offset-Temperature Coefficient (Note 3) Full-Scale Voltage Full-Scale Temperature Coefficient (Note 3) Power-Supply Rejection DC Crosstalk (Note 4) REFERENCE Output Voltage Output-Voltage Temperature Coefficient (Note 3) Reference External Load Regulation Reference Short-Circuit Current DIGITAL INPUTS Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage DYNAMIC PERFORMANCE Voltage-Output Slew Rate SR 0.6 V/s VOH VOL ISOURCE = 2mA ISINK = 2mA 4.25 0.2 V V VIH VIL VHYS IIN CIN Digital inputs = 0 or VDD 8 200 1 0.7 x VDD 0.3 x VDD V V mV A pF VREF TCVREF VOUT/IOUT MAX5231A MAX5231B 0 IOUT 100A (sourcing) 2.465 3 10 0.1 4 2 V ppm/C V/A mA N INL DNL VOS TCVOS VFS TCVFS PSR Code = FFF hex, TA = +25C MAX5231A MAX5231B (Note 6) 4.5V VDD 5.5V 4.070 8 4.095 3 10 175 4.120 10 30 500 100 MAX5231A MAX5231B 12 0.5 1 1 3 Bits LSB LSB mV V/C V ppm/C V V SYMBOL CONDITIONS MIN TYP MAX UNITS
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3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference MAX5230/MAX5231
ELECTRICAL CHARACTERISTICS--MAX5231 (continued)
(VDD = +4.5V to +5.5V, OS_ = AGND = DGND = 0, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Voltage-Output Settling Time Output-Voltage Swing (Note 5) OS_ Input Resistance Time Required for Output to Settle After Turning on VDD (Note 6) Time Required for Output to Settle After Exiting Full Power-Down (Note 6) Time Required for Output to Settle After Exiting DAC Power-Down (Note 6) Digital Feedthrough Major-Carry Glitch Energy POWER SUPPLIES Power-Supply Voltage Power-Supply Current (Note 7) Power-Supply Current in Power-Down and Shutdown Modes (Note 7) VDD IDD Full power-down mode One DAC shutdown mode Both DACs shutdown mode 4.5 470 1.4 350 235 5.5 525 5 390 260 A V A CS = VDD, fSCLK = 100kHz, VSCLK = 5VP-P ROS 83 SYMBOL CONDITIONS To 0.5LSB, VSTEP = 4V (VDD - 0.25V) VOUT 0.25V MIN TYP 10 0 to VDD 121 95 95 12 5 90 400 400 160 MAX UNITS s V k s s s nV-s nV-s
ELECTRICAL CHARACTERISTICS--MAX5230
(VDD = +2.7V to +3.6V, OS_ = AGND = DGND = 0, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity Offset Error (Note 2) Offset-Temperature Coefficient (Note 3) Full-Scale Voltage Full-Scale Temperature Coefficient (Note 3) Power-Supply Rejection DC Crosstalk (Note 4) REFERENCE Output Voltage Output-Voltage Temperature Coefficient (Note 3) VREF TCVREF MAX5230A MAX5230B 1.234 3 10 V ppm/C SYMBOL N INL DNL VOS TCVOS VFS TCVFS PSR Code = FFF hex, TA = +25C MAX5230A MAX5230B (Note 6) 2.7V VDD 3.6V 2.0350 8 2.0475 3 10 175 2.0600 10 30 500 100 MAX5230A MAX5230B CONDITIONS MIN 12 0.5 1 1 3 TYP MAX UNITS Bits LSB LSB mV V/C V ppm/C V V
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3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference MAX5230/MAX5231
ELECTRICAL CHARACTERISTICS--MAX5230 (continued)
(VDD = +2.7V to +3.6V, OS_ = AGND = DGND = 0, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Reference External Load Regulation Reference Short-Circuit Current DIGITAL INPUTS Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage DYNAMIC PERFORMANCE Voltage-Output Slew Rate Voltage-Output Settling Time Output-Voltage Swing (Note 5) OS_ Input Resistance Time Required for Output to Settle After Turning on VDD (Note 6) Time Required for Output to Settle After Exiting Full Power-Down (Note 6) Time Required for Output to Settle After Exiting DAC Power-Down (Note 6) Digital Feedthrough Major-Carry Glitch Energy CS =VDD, fSCLK = 100kHz, VSCLK = 3VP-P ROS 83 SR To 0.5 LSB, VSTEP = 2V (VDD - 0.25V) VOUT 0.25V 0.6 10 0 to VDD 121 95 95 12 5 90 400 400 160 V/s s V k s s s nV-s nV-s VOH VOL ISOURCE = 2mA ISINK = 2mA 2.3 0.25 V V VIH VIL VHYS IIN CIN Digital inputs = 0 or VDD 8 200 1 0.7 x VDD 0.3 x VDD V V mV A pF SYMBOL CONDITIONS MIN TYP 0.1 4 MAX 2 UNITS V/A mA VOUT/IOUT 0 IOUT 100A (sourcing)
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3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference
ELECTRICAL CHARACTERISTICS--MAX5230 (continued)
(VDD = +2.7V to +3.6V, OS_ = AGND = DGND = 0, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER POWER SUPPLIES Power-Supply Voltage Power-Supply Current (Note 7) Power-Supply Current in Power-Down and Shutdown Modes (Note 7) VDD IDD Full power-down mode One DAC shutdown mode Both DACs shutdown mode 2.7 420 0.9 320 220 3.6 475 5 360 245 A V A SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5230/MAX5231
Note 1: Accuracy is guaranteed as shown in the following table:
VDD (V) 3 5 ACCURACY GUARANTEED FROM CODE 20 10 TO CODE 4095 4095
Note 2: Offset is measured at the code closest to 10mV. Note 3: Temperature coefficient is determined by the box method in which the maximum VOUT over the temperature range is divided by T. Note 4: DC crosstalk is measured as follows: set DAC A to midscale, and DAC B to zero, and measure DAC A output; then change DAC B to full scale, and measure VOUT for DAC A. Repeat the same measurement with DAC A and DAC B interchanged. DC crosstalk is the maximum VOUT measured. Note 5: Accuracy is better than 1LSB for VOUT_ = 10mV to VDD - 180mV. Note 6: Guaranteed by design, not production tested. Note 7: RLOAD = and digital inputs are at either VDD or DGND.
TIMING CHARACTERISTICS--MAX5231
(VDD = +4.5V to +5.5V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Figures 1 and 2)
PARAMETER SCLK Clock Period SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time DIN Setup Time DIN Hold Time SCLK Rise to DOUT Valid Propagation Delay Time SCLK Fall to DOUT Valid Propagation Delay Time SCLK Rise to CS Fall Delay CS Rise to SCLK Rise Hold Time CS Pulse Width High LDAC Pulse Width Low CS Rise to LDAC Rise Hold Time SYMBOL tCP tCH tCL tCSS tCSH tDS tDH tDO1 tDO2 tCS0 tCS1 tCSW tLDL tCSLD (Note 8) CLOAD = 200pF CLOAD = 100pF CLOAD = 200pF CLOAD = 100pF 10 30 75 30 40 CONDITIONS MIN 74 30 30 30 0 30 0 45 30 45 30 100 100 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference MAX5230/MAX5231
TIMING CHARACTERISTICS--MAX5230
(VDD = +2.7V to +3.6V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Figures 1 and 2)
PARAMETER SCLK Clock Period SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time DIN Setup Time DIN Hold Time SCLK Rise to DOUT Valid Propagation Delay Time SCLK Fall to DOUT Valid Propagation Delay Time SCLK Rise to CS Fall Delay CS Rise to SCLK Rise Hold Time CS Pulse Width High LDAC Pulse Width Low CS Rise to LDAC Rise Hold Time SYMBOL tCP tCH tCL tCSS tCSH tDS tDH tDO1 tDO2 tCS0 tCS1 tCSW tLDL tCSLD (Note 8) CLOAD = 200pF CLOAD = 100pF CLOAD = 200pF CLOAD = 100pF 10 30 75 30 75 CONDITIONS MIN 74 30 30 30 0 30 0 60 45 60 45 200 200 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 8: This timing requirement applies only to CS rising edges, which execute commands modifying the DAC input register contents.
Typical Operating Characteristics
(VDD = +3V (MAX5230), VDD = +5V (MAX5231), RL = 5k, CL = 100pF, OS_ = AGND, both DACs enabled with full-scale output code, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (MAX5230)
MAX5230/MAX5231 toc01
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (MAX5231)
MAX5230/MAX5231 toc02
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (MAX5230)
MAX5230/MAX5231 toc03
0.15 0.10 0.05 INL (LSB) 0 -0.05 -0.10 -0.15 0
0.15 0.10 0.05 INL (LSB) 0 -0.05 -0.10
0.208
0.086 DNL (LSB)
-0.037
-0.160
-0.283 -0.15 500 1000 1500 2000 2500 3000 3500 4000 DIGITAL INPUT CODE 0 500 1000 1500 2000 2500 3000 3500 4000 DIGITAL INPUT CODE 0 500 1000 1500 2000 2500 3000 3500 4000 DIGITAL INPUT CODE
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3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference
Typical Operating Characteristics (continued)
(VDD = +3V (MAX5230), VDD = +5V (MAX5231), RL = 5k, CL = 100pF, OS_ = AGND, both DACs enabled with full-scale output code, TA = +25C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (MAX5231)
MAX5230/MAX5231 toc04
MAX5230/MAX5231
SUPPLY CURRENT vs. TEMPERATURE (MAX5230)
MAX5230/MAX5231 toc05
SUPPLY CURRENT vs. TEMPERATURE (MAX5231)
MAX5230/MAX5231 toc06
0.15 0.10 0.05 DNL (LSB) 0 -0.05 -0.10 -0.15 0
450
450
440 SUPPLY CURRENT (A)
440 SUPPLY CURRENT (A)
430
430
420
420
410
410
400 500 1000 1500 2000 2500 3000 3500 4000 DIGITAL INPUT CODE -40 -15 10 35 60 85 TEMPERATURE (C)
400 -40 -15 10 35 60 85 TEMPERATURE (C)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX5230)
MAX5230/MAX5231 toc07
SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX5231)
MAX5230/MAX5231 toc08
FULL POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5230)
0.75 SUPPLY CURRENT (A) 0.70 0.65 0.60 0.55 0.50
MAX5230/MAX5231 toc09
430 425 SUPPLY CURRENT (A) 420 415 410 405 400 2.7 3.0 3.3
490 485 SUPPLY CURRENT (A) 480 475 470 465 460
0.80
0.45 0.40 4.50 4.75 5.00 5.25 5.50 -40 SUPPLY VOLTAGE (V) NO LOAD -15 10 35 60 85
3.6
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
TWO-DACs SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5230)
MAX5230/MAX5231 toc10
ONE-DAC SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5230)
MAX5230/MAX5231 toc11
FULL POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5231)
1.1 SUPPLY CURRENT (A) 1.0 0.9 0.8 0.7 0.6
MAX5230/MAX5231 toc12
230 225 SUPPLY CURRENT (A) 220 215 210 205 NO LOAD 200 -40 -15 10 35 60
330 325 SUPPLY CURRENT (A) 320 315 310 305 NO LOAD 300
1.2
0.5 NO LOAD 0.4 -40 -15 10 35 60 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C)
85
TEMPERATURE (C)
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3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference MAX5230/MAX5231
Typical Operating Characteristics (continued)
(VDD = +3V (MAX5230), VDD = +5V (MAX5231), RL = 5k, CL = 100pF, OS_ = AGND, both DACs enabled with full-scale output code, TA = +25C, unless otherwise noted.)
TWO-DACs SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5231)
MAX5230/MAX5231 toc13
ONE-DAC SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5231)
MAX5230/MAX5231 toc14
FULL-SCALE OUTPUT VOLTAGE vs. TEMPERATURE (MAX5230)
MAX5230/MAX5231 toc15
255 250 SUPPLY CURRENT (A) 245 240 235 230 NO LOAD 225 -40 -15 10 35 60
380 375 SUPPLY CURRENT (A) 370 365 360 355 NO LOAD 350
2.0480 FULL-SCALE OUTPUT VOLTAGE (V)
2.0475
2.0470
2.0465 NO LOAD 2.0460
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
FULL-SCALE OUTPUT VOLTAGE vs. TEMPERATURE (MAX5231)
MAX5230/MAX5231 toc16
FULL-SCALE ERROR vs. RESISTIVE LOAD (MAX5230)
MAX5230/MAX5231 toc17
FULL-SCALE ERROR vs. RESISTIVE LOAD (MAX5231)
MAX5230/MAX5231 toc18
4.0940 FULL-SCALE OUTPUT VOLTAGE (V) 4.0935 4.0930 4.0925 4.0920 4.0915 NO LOAD 4.0910 -40 -15 10 35 60
0.35 0.30 FULL-SCALE ERROR (LSB) 0.25 0.20 0.15 0.10 0.05 0 CHANGE FROM NO LOAD 2.5 3.5 4.5 5.5 6.5
0.25
FULL-SCALE ERROR (LSB)
0.20
0.15
0.10
0.05 CHANGE FROM NO LOAD 2.5 3.5 4.5 5.5 6.5 7.5
0 7.5
85
TEMPERATURE (C)
RESISTIVE LOAD (k)
RESISTIVE LOAD (k)
DYNAMIC RESPONSE RISE TIME (MAX5230)
MAX5230/MAX5231 toc19
DYNAMIC RESPONSE RISE TIME (MAX5231)
MAX5230/MAX5231 toc20
DYNAMIC RESPONSE FALL TIME (MAX5230)
MAX5230/MAX5231 toc21
VCS 2V/div
3V VCS 5V/div 0 2.048V 5V 0 4.096V VCS 2V/div
3V 0 2.048V
VOUT 500mV/div 10mV 2s/div
VOUT 1V/div 10mV 2s/div
VOUT 500mV/div 10mV 2s/div
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3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference
Typical Operating Characteristics (continued)
(VDD = +3V (MAX5230), VDD = +5V (MAX5231), RL = 5k, CL = 100pF, OS_ = AGND, both DACs enabled with full-scale output code, TA = +25C, unless otherwise noted.)
DYNAMIC RESPONSE FALL TIME (MAX5231)
MAX5230/MAX5231 toc22
MAX5230/MAX5231
ANALOG CROSSTALK (MAX5230)
MAX5230/MAX5231 toc23
ANALOG CROSSTALK (MAX5231)
MAX5230/MAX5231 toc24
VCS 5V/div
5V 0 4.096V
OUTA 2V/div
OUTA 5V/div
VOUT 1V/div 10mV 2s/div
OUTB 5mV/div AC-COUPLED
OUTB 5mV/div AC-COUPLED
400s/div
400s/div
DIGITAL FEEDTHROUGH (MAX5230)
MAX5230/MAX5231 toc25
DIGITAL FEEDTHROUGH (MAX5231)
MAX5230/MAX5231 toc26
MAJOR-CARRY TRANSITION (MAX5230)
MAX5230/MAX5231 toc27
SCLK 2V/div
SCLK 5V/div
CS 5V/div
OUTA 1mV/div AC-COUPLED
OUTA 1mV/div AC-COUPLED
OUTA 100mV/div AC-COUPLED
10s/div
10s/div
2s/div
MAJOR-CARRY TRANSITION (MAX5231)
MAX5230/MAX5231 toc28
REFERENCE VOLTAGE vs. TEMPERATURE (MAX5230)
MAX5230/MAX5231 toc29
REFERENCE VOLTAGE vs. TEMPERATURE (MAX5231)
MAX5230/MAX5231 toc30
1.2350
2.4630
REFERENCE VOLTAGE (V)
1.2345
REFERENCE VOLTAGE (V)
CS 5V/div
2.4625
1.2340
2.4620
OUTA 100mV/div AC-COUPLED
1.2335 NO LOAD 1.2330
2.4615 NO LOAD 2.4610
2s/div
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
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3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference MAX5230/MAX5231
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME OSA OUTA RSTV LDAC CLR CS DIN SCLK DGND DOUT PDL REF AGND VDD OUTB OSB DAC A Offset Adjust DAC A Output Reset Value Input 1: Connect to VDD to select midscale as the reset value. 0: Connect to DGND to select zero as the reset value. Load DACs A and B Clear Input. Both DAC outputs go to zero or midscale. Clears both DAC internal registers (input register and DAC register) to its predetermined (RSTV) state. Chip-Select Input Serial Data Input. Data is clocked in on the rising edge of SCLK. Serial Clock Input Digital Ground Serial Data Output Power-Down Lockout. Disables shutdown of both DACs when low. Reference Output. Reference provides a 2.465V (MAX5231) or 1.234V (MAX5230) nominal output. Analog Ground Positive Power Supply. Bypass VDD with a 0.1F capacitor in parallel with a 4.7F capacitor to AGND, and bypass VDD with a 0.1F capacitor to DGND. DAC B Output DAC B Offset Adjust FUNCTION
CS
COMMAND EXECUTED
SCLK 1 DIN DOUT (MODE 0) DOUT (MODE 1) C2 C1 C0 D11 D10 D9 D8 8 D7 D6 9 D5 D4 D3 D2 D1 D0 16 S0 C2 C2 C1 C1 (1)
Figure 1. Serial Interface Timing
10
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3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference MAX5230/MAX5231
tLDL tCSLD LDAC tCSW CS tCSO SCLK tCH tCP DIN tDS DOUT tD01 tD02 tDH tCL tCSS tCSH tCS1
Figure 2. Detailed Serial Interface Timing
Detailed Description
The MAX5230/MAX5231 12-bit, voltage-output DACs are easily configured with a 3-wire SPI-, QSPI-, MICROWIRE-compatible serial interface. The devices include a 16-bit data-in/data-out shift register and have an input consisting of an input register and a DAC register. In addition, these devices employ precision trimmed internal resistors to produce a gain of 1.6384V/V, maximizing the output voltage swing, and a programmable-shutdown output impedance of 1k or 200k The full-scale output voltage is 4.095V for the MAX5231 and 2.0475V for the MAX5230. These devices produce a weighted output voltage proportional to the digital input code with an inverted Rail-to-Rail(R) ladder network (Figure 3).
0.6V/s and settle to 1/2LSB within 10s with a load of 5k in parallel with 100pF. Use the serial interface to set the shutdown output impedance of the amplifiers to 1k or 200k. OS_ can be used to produce an offset voltage at the output. For instance, to achieve a 1V offset, apply -1V to OS_ to produce an output range from 1V to (1V + VFS/VREF). Note that the DAC's output range is still limited by the maximum output voltage specification.
OS_ 121k
77.25k
Internal Reference
The MAX5230/MAX5231 use an on-board precision bandgap reference to generate an output voltage of 1.234V (MAX5230) or 2.465V (MAX5231). With a low temperature coefficient of only 3ppm/C, REF can source up to 100A and is stable for capacitive loads less than 35pF. The output amplifiers have internal resistors that provide for a gain of 1.6384V/V when OS_ is connected to AGND. The output amplifiers have a typical slew rate of
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
R
R
R
OUT_
2R
2R D0
2R D9
2R D10
2R D11 1k
Output Amplifiers
REF AGND SHOWN FOR ALL ONES ON DAC
Figure 3. Simplified DAC Circuit Diagram 11
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3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference MAX5230/MAX5231
Table 1. Serial Data Format
MSB <------------16-bits of serial data ------------> LSB 3 Control Bits C2...C0 MSB .. 12 Data Bits ... LSB D11 ..............................D0 Sub-Bit S0
ously. The control bits and D11-D8 allow the DACs to operate independently. Send the 16-bit data as one 16-bit word (QSPI) or two 8-bit packets (SPI, MICROWIRE), with CS low during this period. The control bits and D11-D8 determine which registers update and the state of the registers when exiting shutdown. The 3-bit control and D11-D8 determine the following: * Registers to be updated * Selection of the power-down and shutdown modes The general timing diagram of Figure 1 illustrates data acquisition. Driving CS low enables the device to receive data. Otherwise the interface control circuitry is disabled. With CS low, data at DIN is clocked into the register on the rising edge of SCLK. As CS goes high, data is latched into the input and/or DAC registers, depending on the control bits and D11-D8. The maximum clock frequency guaranteed for proper operation is 13.5MHz. Figure 2 depicts a more detailed timing diagram of the serial interface.
Serial Interface
The 3-wire serial interface (SPI, QSPI, MICROWIRE compatible) used in the MAX5230/MAX5231 allows for complete control of DAC operations (Figures 4 and 5). Figures 1 and 2 show the timing for the serial interface. The serial word consists of 3 control bits followed by 12 data bits (MSB first) and 1 sub-bit as described in Tables 1, 2, and 3. When the 3 control bits are all zero or all 1, D11-D8 are used as additional control bits, allowing for greater DAC functionality. The digital inputs allow any of the following: loading the input register(s) without updating the DAC register(s), updating the DAC register(s) from the input register(s), or updating the input and DAC register(s) simultane-
Table 2. Serial-Interface Programming Commands
16-BIT SERIAL WORD C2 0 0 0 1 1 1 1 0 C1 0 1 1 0 0 1 1 0 C0 1 0 1 0 1 0 1 0 D11..............D0 12-bit DAC data 12-bit DAC data 12-bit DAC data XXXXXXXXXXXX 12-bit DAC data 12-bit DAC data P1A P1B X X X X X X X X X X 001XXXXXXXXX S0* 0 0 0 0 0 0 0 0 FUNCTION Load input register A; DAC registers are unchanged. Load input register A; all DAC registers are updated. Load all DAC registers from the shift register (start up both DACs with new data, and load the input registers). Update both DAC registers from their respective input registers (start up both DACs with data previously stored in the input registers). Load input register B; DAC registers are unchanged. Load input register B; all DAC registers are updated. Shut down both DACs, respectively, according to bits P1A and P1B (see Table 3). Internal bias and reference remain active. Update DAC register A from input register A (start up DAC A with data previously stored in input register A). Full Power-Down. Power down the main bias generator and shut down both DACs, respectively, according to bits P1A and P1B (see Table 3). Update DAC register B from input register B (start up DAC B with data previously stored in input register B). Shut down DAC A according to bit P1A (see Table 3). Shut down DAC B according to bit P1B (see Table 3). Mode 0. DOUT clocked out on SCLK falling edge (default). Mode 1. DOUT clocked out on SCLK rising edge.
0
0
0
0 1 1 P1A P1B X X X X X X X
0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
101XXXXXXXXX 1 1 0 P1A X X X X X X X X 1 1 1 P1B X X X X X X X X 1000XXXXXXXX 1001XXXXXXXX
0 0 0 0 0
X = Don't care. * S0 must be zero for proper operation. 12 ______________________________________________________________________________________
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference
Power-Down and Shutdown Modes
As described in Tables 2 and 3, several serial interface commands put one or both of the DACs into shutdown mode. Shutdown modes are completely independent for each DAC. In shutdown, the amplifier output becomes high impedance, and OUT_ terminates to OS_ through the 200k (typ) gain resistors. Optionally (see Tables 2 and 3), OUT_ can have an additional termination of 1k to AGND. Full power-down mode shuts down the main bias generator, reference, and both DACs. The shutdown impedance of the DAC outputs can still be controlled independently, as described in Tables 2 and 3. A serial interface command exits shutdown mode and updates a DAC register. Each DAC can exit shutdown at the same time or independently (see Tables 2 and 3). For example, if both DACs are shut down, updating the DAC A register causes DAC A to power up, while DAC B remains shut down. In full power-down mode, powering up either DAC also powers up the main bias generator and reference. To change from full powerdown to both DACs shutdown requires the waking of at least one DAC between states. When powering up the MAX5230/MAX5231 (powering VDD), allow 400s (max) for the output to stabilize. When exiting full power-down mode, also allow 400s (max) for the output to stabilize. When exiting DAC shutdown mode, allow 160s (max) for the output to stabilize.
MAX5230/MAX5231
5V
SS DIN MOSI
MAX5230 MAX5231
SCLK
SCK
SPI/QSPI PORT
CS
I/O
Figure 4. SPI/QSPI Interface Connections
SCLK
SK
MAX5230 MAX5231
DIN
SO
MICROWIRE PORT
CS
I/O
Reset Value (RSTV) and Clear (CLR) Inputs
Driving CLR low asynchronously forces both DAC outputs and all the internal registers (input registers and DAC registers) for both DACs to either zero or midscale, depending on the level at RSTV. RSTV = DGND sets the zero value, and RSTV, = VDD sets the midscale value. The internal power-on reset circuit sets the DAC outputs and internal registers to either zero or midscale when power is first applied to the device, depending on the level at RSTV as described in the preceding paragraph. The DAC outputs are enabled after power is first applied. In order to obtain the midscale value on power-up (RSTV = VDD), the voltage on RSTV must rise simultaneously with the VDD supply.
Figure 5. Connections for MICROWIRE
Load DAC Input (LDAC)
Asserting LDAC asynchronously loads the DAC registers from their corresponding input registers (DACs that are shut down remain shut down). The LDAC input is totally asynchronous and does not require any activity on CS, SCLK, or DIN in order to take effect. If LDAC is asserted coincident with a rising edge of CS, which executes a serial command modifying the value of either DAC input register, then LDAC must remain asserted for at least 30ns following the CS rising edge. This requirement applies only for serial commands that modify the value of the DAC input registers.
Power-Down Lockout Input (PDL)
Driving PDL low disables shutdown of either DAC. When PDL is low, serial commands to shut down either DAC are ignored. When either DAC is in shutdown mode, a highto-low transition on PDL brings the DACs and the reference out of shutdown with DAC outputs set to the state prior to shutdown.
Table 3. P1 Shutdown Modes
P1 (A/B) 0 1 SHUTDOWN MODE Shut down with internal 1k load to GND Shut down with internal 200k load to GND
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13
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference MAX5230/MAX5231
Applications Information
Definitions
Integral Nonlinearity (INL) Integral nonlinearity (Figure 6a) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every single step. Differential Nonlinearity (DNL) Differential nonlinearity (Figure 6b) is the difference between an actual step height and the ideal value of 1LSB. If the magnitude of the DNL is less than 1LSB, the DAC guarantees no missing codes and is monotonic.
7 ANALOG OUTPUT VALUE (LSB) ANALOG OUTPUT VALUE (LSB) 6 5 4 3 2 1 0 000 001 010 011 100 101 110 111 DIGITAL INPUT CODE AT STEP 001 (1/4LSB ) AT STEP 011 (1/2LSB )
Offset Error The offset error (Figure 6c) is the difference between the ideal and the actual offset point. For a DAC, the offset point is the step value when the digital input is zero. This error affects all codes by the same amount and can usually be compensated for by trimming. Gain Error Gain error (Figure 6d) is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Settling Time The settling time is the amount of time required from the start of a transition, until the DAC output settles to its new output value within the converter's specified accuracy.
6 5 4 3 1LSB 2 1 0 000 001 010 011 100 101 DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR (+1/4LSB) 1LSB DIFFERENTIAL LINEARITY ERROR (-1/4LSB)
Figure 6a. Integral Nonlinearity
Figure 6b. Differential Nonlinearity
IDEAL FULL-SCALE OUTPUT GAIN ERROR (-1 1/4LSB) 6 IDEAL DIAGRAM 5 ACTUAL FULL-SCALE OUTPUT
3 ANALOG OUTPUT VALUE (LSB)
2 IDEAL DIAGRAM 1
0
ACTUAL OFFSET OFFSET ERROR POINT (+1 1/4LSB) IDEAL OFFSET POINT 000 001 010 011 DIGITAL INPUT CODE
ANALOG OUTPUT VALUE (LSB)
ACTUAL DIAGRAM
7
4 0 000 100 101 110 111 DIGITAL INPUT CODE
Figure 6c. Offset Error 14
Figure 6d. Gain Error
______________________________________________________________________________________
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference
Table 4. Unipolar Code Table
V+
MAX5230/MAX5231
DAC CONTENTS MSB 1111 1111 1 1000 0000 0 1000 0000 0 0111 1111 1 0000 0000 0000 0000 0 LSB 111 (0) 001 (0) 000 (0) 111 (0) 001 (0) 000 (0)
ANALOG OUTPUT (V) MAX5230 2.04750 1.02425 1.02375 1.02325 0.00050 0 MAX5231 4.0950 2.0485 2.0475 2.0465 0.0010 0
REF
5V/3V VDD REF 121k OS_
PHOTODIODE
V+ 77.25k DAC_ OUT_ V-
VOUT
Digital Feedthrough Digital feedthrough is noise generated on the DAC's output when any digital input transitions. Proper board layout and grounding significantly reduce this noise, but there is always some feedthrough caused by the DAC itself.
MAX5230 MAX5231
AGND DGND
1k
RPULLDOWN
Unipolar Output
Figure 7 shows the MAX5230/MAX5231 configured for unipolar, rail-to-rail operation. The MAX5231 produces a 0 to 4.095V output, while the MAX5230 produces 0 to 2.0475V output. Table 4 lists the unipolar output codes.
Figure 8. Digital Calibration
Digital Calibration and Threshold Selection
Figure 8 shows the MAX5230/MAX5231 in a digital calibration application. With a bright light value applied to the photodiode (on), the DAC is digitally ramped until it trips the comparator. The microprocessor (P) stores this "high" calibration value. Repeat the process with a dim light (off) to obtain the dark current calibration. The P then programs the DAC to set an output voltage at the midpoint of the two calibrated values. Applications include tachometers, motion sensing, automatic readers, and liquid clarity analysis.
REF
5V/3V VDD REF 121k OS_
77.25k DAC_ OUT_
Sharing a Common DIN Line
Several MAX5230/MAX5231s may share one common DIN signal line (Figure 9). In this configuration, the data bus is common to all devices; data is not shifted through a daisy-chain. The SCLK and DIN lines are shared by all devices, but each IC needs its own dedicated CS line.
MAX5230 MAX5231
AGND GAIN = 1.6384V/V DGND
1k
Daisy-Chaining Devices
Any number of MAX5230/MAX5231s can be daisychained by connecting the serial data output (DOUT) of one device to the digital input (DIN) of the following device in the chain (Figure 10).
Figure 7. Unipolar Output Circuit (Rail-to-Rail)
______________________________________________________________________________________
15
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference MAX5230/MAX5231
DIN SCLK CS1 CS2 CS3
TO OTHER SERIAL DEVICES
CS
CS
CS
MAX5230 MAX5231
SCLK DIN SCLK DIN
MAX5230 MAX5231
SCLK DIN
MAX5230 MAX5231
Figure 9. Multiple MAX5230/MAX5231s Sharing a Common DIN Line
SCLK CS CS CS CS
TO OTHER SERIAL DEVICES
MAX5230 MAX5231
SCLK DIN DIN DOUT
MAX5230 MAX5231
SCLK DIN DOUT
MAX5230 MAX5231
SCLK DIN DOUT
Figure 10. Daisy-Chaining MAX5230/MAX5231 Devices
Power-Supply and Bypassing Considerations
On power-up, the input and DAC registers are cleared to either zero (RSTV = DGND) or midscale (RSTV = VDD). Bypass VDD with a 4.7F capacitor in parallel with a 0.1F capacitor to AGND, and bypass VDD with a 0.1F capacitor to DGND. Minimize lead lengths to reduce lead inductance.
grounding techniques, such as a multilayer board with a low-inductance ground plane or star connect all ground return paths back to the MAX5230/MAX5231 AGND. Carefully lay out the traces between channels to reduce AC cross-coupling and crosstalk. Wire-wrapped boards and sockets are not recommended. If noise becomes an issue, shielding may be required.
Grounding and Layout Considerations
Digital and AC transient signals on AGND or DGND can create noise at the output. Connect AGND and DGND to the highest quality ground available. Use proper
Chip Information
TRANSISTOR COUNT: 4745 PROCESS: BiCMOS
16
______________________________________________________________________________________
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference MAX5230/MAX5231
Functional Diagram
CS
DIN SCLK
DOUT
VDD
AGND
DGND 121k OSA 77.25k
DAC A PDL SR CONTROL 16-BIT SHIFT REGISTER
AMP A 1k
OUTA
LDAC RSTV CLR 1
1k SHUTDOWN DECODE CONTROL 121k OSB 77.25k INPUT REGISTERS DAC REGISTER DAC B AMP B OUTB
1k SHUTDOWN BANDGAP REFERENCE 1.25V 2X (1X) 2.5V (1.25V) REFERENCE BUFFER MAX5230 MAX5231
( ) FOR MAX5230 ONLY REF
______________________________________________________________________________________
17
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference MAX5230/MAX5231
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
21-0055
E
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
QSOP.EPS

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